256k x 8 static ram cy62138vn mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06513 rev. ** revised february 2, 2006 features ? temperature ranges ? industrial: ?40c to 85c ? low voltage range: ? 2.7?3.6v ? ultra-low active power ? low standby power ? easy memory expansion with cs 1 /cs 2 and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected ? cmos for optimum speed/power ? offered in standard non-lead-free 36-ball fbga package functional description the cy62138vn is a high-per formance cmos static ram organized as 256k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that reduces power consumption by 99% when addr esses are not toggling. the device can be put into standby mode when deselected (cs 1 high or cs 2 low). writing to the device is accomplished by taking chip enable one (cs 1 ) and write enable (we ) inputs low and chip enable two (cs 2 ) high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 17 ).reading from the device is accomplished by taking chip enable one (cs 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (cs 2 ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins.the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (cs 1 high or cs 2 low), the outputs are disabled (oe high), or during a write operation (cs 1 low, cs 2 high, and we low). 14 15 pi n c on fi gura ti on a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 cs 2 i/o 1 i/o 2 i/o 3 256k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 cs 1 a a 16 a 9 17 a a v cc a 13 a 12 a 5 cs 2 we a 7 i/o 4 i/o 5 a 4 nc i/o 6 i/o 7 v ss a 11 a 10 a v ss i/o 0 a a 8 a 6 a 3 a v cc i/o 1 i/o 2 i/o 3 a 17 nc a 16 cs oe a 9 a 14 36 5 4 d e b a c f g h top view fbga 12 1 15 0 1 2 l og i c bl oc k di agram product portfolio product v cc range speed power dissipation (industrial) operating (i cc ) standby (i sb2 ) v cc(min) v cc(typ) [1] v cc(max) typ. [1] maximum typ. [1] maximum cy62138vn 2.7v 3.0v 3.6v 70 ns 7 ma 15 ma 1 a 15 a note: 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc typ, t a = 25c. [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] ................................ ?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range device range ambient temperature v cc cy62138vn industrial ?40c to +85c 2.7v to 3.6v electrical characteristics over the operating range parameter description test conditions cy62138vn unit min. typ. [1] max. v oh output high voltage i oh = -1.0 ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 v v ih input high voltage v cc = 3.6v 2.2 v cc + 0.5v v v il input low voltage v cc = 2.7v ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 +1 a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc, cmos levels v cc = 3.6v 7 15 ma i out = 0 ma, f = 1 mhz, cmos levels 1 2 ma i sb1 automatic ce power-down current? cmos inputs ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = f max v cc = 3.6v 100 a i sb2 automatic ce power-down current? cmos inputs ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = 0 v cc = 3.6v 1 15 a capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 6 pf c out output capacitance 8 pf notes: 2. v il (min) = ?2.0v for pulse durations less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 3 of 8 ac test loads and waveforms notes: 4. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to v cc typ., and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. ce is the combination of both cs 1 and cs 2 . parameters value unit r1 1105 ohms r2 1550 ohms r th 645 ohms v th 1.75 volts data retention characteristics (over the operating range) parameter description conditions [4] min. typ. [1] max. unit v dr v cc for data retention 1.0 3.6 v i ccdr data retention current v cc = 1.0v ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v no input may exceed v cc +0.3v 0.1 5 a t cdr [3] chip deselect to data retention time 0 ns t r operation recovery time 100 ms data retention waveform [5] v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% <5ns <5 ns output v equivalent to: th venin equivalent all input pulses rth r1 v cc(min.) v cc(min.) t cdr v dr > 1.0v data retention mode t r ce v cc [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 4 of 8 switching characteristics over the operating range [4] parameter description cy62138vn unit min. max. read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low-z [6] 5 ns t hzoe oe high to high-z [6, 7] 25 ns t lzce ce low to low-z [6] 10 ns t hzce ce high to high-z [6, 7] 25 ns t pu ce low to power-up 0 ns t pd ce high to power-down 70 ns write cycle [8, 9] t wc write cycle time 70 ns t sce ce low to write end 60 ns t aw address set-up to write end 60 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t sd data set-up to write end 30 ns t hd data hold from write end 0 ns t hzwe we low to high-z [6, 7] 25 ns t lzwe we high to low-z [6] 10 ns switching waveforms read cycle no. 1 [10, 11] notes: 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 10. device is continuously selected. oe , ce = v il . 11. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 5 of 8 read cycle no. 2 [5., 11, 12] write cycle no. 1 (we controlled) [5, 8, 13, 14] write cycle no. 2 (ce controlled) [5, 8, 13, 14] notes: 12. address valid prior to or coincident with ce transition low. 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 15. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 15 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 6 of 8 write cycle no. 3 (we controlled, oe low) [5, 9, 14] switching waveforms (continued) data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 15 typical dc and ac characteristics ? 55 25 105 2.5 2.0 1.5 current vs. ambient temperature ambient temperature ( c) 1.0 0.5 0.0 ?0.5 i sb 3.0 standby v cc = v cc typ. v in = v cc typ. i sb2 a 1.50 1.00 0.50 1 15 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.10 10 5 1.2 1.4 1.0 0.6 0.4 0.2 1.0 1.9 2.8 3.7 supply voltage (v) normalized standby current vs. supply voltage 0.0 0.8 normalized i sb i sb2 1.2 1.4 1.0 0.6 0.4 0.2 1.7 2.2 2.7 3.2 3.7 supply voltage (v) normalized supply current vs. supply voltage 0.0 0.8 normalized i cc i cc v in = v cc typ. t a = 25 c v in = v cc typ. t a = 25 c v cc = 3.3v [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram more battery life is a trademark, and mobl is a registered trademark, of cypress semiconductor. all products and company names mentioned in this document may be t he trademarks of their respective holders. truth table cs 1 cs 2 we oe inputs/outputs mode power h x x x high-z deselect/power-down standby (i sb ) x l x x high-z deselect/power-down standby (i sb ) l h h l data out read active (i cc ) l h l x data in write active (i cc ) l h h h high-z deselect, output disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 70 CY62138VNLL-70BAI 51-85099 36-ball (7.0 mm 7.0 mm 1.2 mm) fbga industrial please contact your local cypress sales repres entative for availability of other parts 36-ball fbga (7 x 7 x 1.2 mm) (51-85099) 51-85099-*c [+] feedback [+] feedback
cy62138vn mobl ? document #: 001-06513 rev. ** page 8 of 8 document history page document title: cy62138vn mobl ? 256k x 8 static ram document number: 001-06513 rev. ecn no. issue date orig. of change description of change ** 426504 see ecn nxr new data sheet [+] feedback [+] feedback
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